The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to methods for forming non-mandrel cuts.
A back-end-of-line (BEOL) interconnect structure may be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing. The metallization levels of a BEOL interconnect structure may be formed using a damascene process. In a dual damascene process, via openings and trenches are formed in a dielectric layer and simultaneously filled with metal to create a metallization level. In a single-damascene process, the via openings and trench are separately formed and filled with metal.
Self-aligned patterning processes involve the use of mandrels as sacrificial structures to set a feature pitch. Sidewall spacers, which have a thickness less than that permitted by the current ground rules for optical lithography, are formed on the vertical sidewalls of the mandrels. After selective removal of the mandrels, the sidewall spacers are used as an etch mask to etch an underlying hardmask and dielectric layer, for example, with a directional reactive ion etch (RIE) process.
Cuts may be formed in mandrels with a cut mask and etching in order to section the mandrels and define gaps that subsequently are used to form adjacent wires that are spaced apart at their tips with a tip-to-tip spacing. A pattern reflecting the cut mandrels is transferred to a hardmask, which is used in turn to pattern a dielectric layer. Non-mandrel cuts may also be formed in the hardmask itself and filled by spacer material when the sidewall spacers are formed on the mandrels. These non-mandrel cuts are also transferred to the hardmask and subsequently from the hardmask to the patterned dielectric layer.
Improved methods of forming non-mandrel cuts are needed.